1. Field of the Invention
The present invention relates to the accessing of items of architectural state within a data processing apparatus.
2. Description of the Prior Art
The data processing apparatus will have architectural state associated therewith. Typically, some architectural state is associated with each instruction executed by a functional unit within the data processing apparatus, whilst other architectural state will relate to overall operational status of the functional unit or units within the data processing apparatus. Within such a data processing apparatus, it is known to provide certain items of architectural state within a plurality of registers. When a functional unit within the data processing apparatus needs to perform a processing operation with reference to one of those items of architectural state, then it will typically access the relevant register via an access port associated with the plurality of registers. Hence, the plurality of registers, which may for example be formed as a bank of registers, will typically have a predetermined number of write ports associated therewith and a predetermined number of read ports associated therewith. Hence, a functional unit can retrieve an item of architectural state from a particular register via a read port, and can write an item of architectural state to a particular register via a write port.
As data processing apparatus become more complex, the number of functional units within the data processing apparatus is tending to increase. For example, the data processing apparatus may be provided with a separate load/store unit, arithmetic logic unit, multiply, unit, etc and may support multiple instruction issue or concurrent execution of different instructions within those multiple functional units. This increase in complexity increases the demand placed on the access ports, and particularly the read ports, associated with the plurality of registers. In particular, as the instruction issue rate of a processor is sought to be increased, it becomes increasingly important for an instruction's operand(s) to be available promptly. For register-based operands, this places increasing demands on the availability of read ports in the register file containing the plurality of registers.
One approach for reducing this demand is to increase the number of read ports, but each read port has an associated cost in terms of gate count, area and signal loading.
Accordingly, it is an object of the present invention to provide a technique which allows such demand on the read ports to be alleviated.